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| ASM5206C/6306C DATA SHEET ASM5206C/6306C ASM5206C/6306C - 1.0 General Description The ASM5206C/6306C is very low cost voice synthesizer with 4-bit microprocessor. It has various features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle, except for program branches and data table read instructions (which need two instruction cycles). 1.1 Feature Single power supply can operate from 2.4V through 5.5V Internal Program ROM: 4K x 10-bit 1 sets of 18-bit DPR can access up to 192K x 10 bits data memory space Data Registers: * 64 x 4-bit data RAM (00-1Fh plus 40h-5Fh) * Unbanked special function registers (SFR) range: 20h-3Fh I/O Ports: * PRA: 4-bit I/O Port A (2Bh) * PRB: 2-bit Output Port B (2Dh) On-chip clock generator: Resistive Clock Drive(RM) Timer: 1 * Timer0: a 9-bit auto-reload timer/counter Stack: 2-level subroutine nesting HALT and Release from HALT function to reduce power consumption Watch Dog Timer (WDT) Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles Number of instruction: 22 The Voice function can be implemented by microprocessor instruction * One 8-bit COUT output for ASM5206C/6306C VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR 1 Rev 1.0 ASM5206C/6306C FIGURE 1.1 : Block Diagram of ASM5206C/6306C Data Bus[3:0] ROM Latch PCL(4) PC[11:0] (ADDR[17:12]) =00000b ADDR[17:0] Stack(12) (2-Level) 0 ROM_ADDR[17:0] 1 DPR3,2,1 DPR[17:0] Program (Data) ROM Instruction Latch Instruction Bus [9:0] Instruction Decoder PCLATCH(8) PCH(8) DLATCH(10) ROM_Data[9:0] Data Bus[3:0] Accumlator(4) Instruction Bus [9:0] SRAM ALU(4) Register(4) Immediate(4) (64 x 4) 00h-1Fh 40h-5Fh Timer0(9) PRA(4) PRB(2) P1,P2,P3,P4 enter test mode ( Voice synthesizer ) Clock Generator Test select Power on Reset RESET pin PRA0 weak or strong pull-low for PRA, PRB, PRC OSC VDD/GND PRASL(4) One-Channel Reset Chip Reset Chip COUT COUT 2 Rev 1.0 Instruction Bus [9:0] Control Signal ASM5206C/6306C FIGURE 1.2 : External ROM Map of ASM5206C/6306C PC[11:0] 12bit x 2 STACK 17-bit Data Pointer Reset Vector 00000h 00080h Reserved for Testing Program and data ROM 00080h-003FFh 00400h 00000h-00FFFh 00000h-2FFFFh 00FFFh(4K) Data ROM 2FFFFh(192Kx10-bits) 3 Rev 1.0 ASM5206C/6306C 1.2 Pin-Out ASM5206C/6306C Pin-Out VDD PRA3-1 PRA0/RESET I I/O I/O Power supply during operation STI I/O port with programmable strong pull-low or weak pull-low or fix-inputStd./O.D. floating capability Output type with standard or Open-Drain output STI I/O port with programmable strong pull-low or weak pull-low or fix-inputStd./O.D. floating capability Output type with standard or Open-Drain output Mask option selected as an external RESET pin with weak pull-low capability RM mode Oscillator input Current Output of Audio Circuit Ground Potential Enter Test Mode. ( TEST = High ) Std./O.D. Output type with standard or Open-Drain output OSC COUT GND TEST PRB0-1 I O I O O 1.3 Application circuit 4 Rev 1.0 ASM5206C/6306C 1.4 Bonding Diagram 192K x 10 bit ROM 1 2 3 4 5 ASM5206C/6306C CHIP SIZE: X= 1550+80(um) , Y= 2700+80(um) 11 10 8 9 6 7 Substrate must be connected to GND. ASM5206C/6306C Pad Location CHIP SIZE: X= 1550+80(um) , Y= 2700+80(um) PAD # PAD Name X Y PAD # PAD Name X Y 1 RA3 -664.92 -944.32 7 TEST_PAD 105.44 -1269 2 RA2 -664.92 -1072.44 8 COUT 303.96 -1269 3 RA1 -662.64 -1269 9 VDD 683.04 -1269 4 RA0 -468.24 -1269 10 RB0 664.92 -1068 5 OSC -281.04 -1269 11 RB1 664.92 -949.6 6 GND -111.72 -1269 5 Rev 1.0 ASM5206C/6306C 1.5 DC Characteristics for ASM5206C/6306C SYMBOL VDD Isb Iop Iih Ioh Iol Cout dF/F dF/F PARAMETER OPERATING VOLTAGE SUPPLY CURRENT STANDBY OPERATING VDD 3 5 3 5 3 5 5 3 5 3 5 3 5 -10 -20 MIN. 2.4 TYP. 3 MAX. 5.5 1 1 UNIT V uA mA uA CONDITION depending on Freq. 4MHz, RM in HALT Mode 4MHz, RM IO Floating 4MHz, RM in HALT Mode (IO Ports with weak pull-high pull-low) INPUT CURRENT /Internal pull low OUTPUT HIGH CURRENT OUTPUT LOW CURRENT DA CURRENT OUT (FULL SCALE) FREQUENCY STABILITY Fosc VARIATION 2 7 3 9 -5.2 -3 -8 7 20 4 5.2 10 20 mA 4MHz, RM (IO ports) % % Fosc(3v- 2.4v) Fosc (3v) VDD=3V, Rosc=820k, 4MHz FIGURE 1.3 : Frequency Range for Rosc in RM mode Resistor(k ohm) 3v Freq.(MHz) 1000 3.66 820 4 560 6.2 470 7.16 R o sc & Fre q . 8 Freq. MHz 6 4 2 0 0 200 400 600 R o sc k o h m 800 1000 1200 7 .1 6 6 .2 4 3 .6 6 6 Rev 1.0 |
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